1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a structure and method for self-aligning a buried strap diffusion to a gate conductor edge of a vertical transistor for semiconductor memories.
2. Description of the Related Art
Since the scalability of planar transistors (such as, metal oxide semiconductor field effect transistors or MOSFETs) in trench storage memory devices is severely limited, memory cells have looked toward utilization of vertical transistors. Vertical transistors are promising candidates for scalability, especially below minimum feature sizes of 100nm. This is due in part to the vertical channel length for the vertical transistors being decoupled from the minimum design ground rule. However, as with all new technologies, opportunities exist for improving the structure and process integration of these cells.
Referring to FIG. 1, one area for improvement concerns the properties of a buried-strap outdiffusion 12 between a trench capacitor 14 and a vertical transistor 16. The buried-strap outdiffusion 12 should be limited to avoid back-to-back device interaction where buried-strap outdiffusions face each other in adjacent cells (See FIG. 1). The distance between back-to-back strap outdiffusion is characterized by a parameter Xs in FIG. 1. For a given cell design and set of design groundrules, it is desired to maximize Xs. This means that the strap outdiffusion 12 into a deep trench 18 (DT) sidewall should be minimized. This is indicated by a parameter BSODx as shown in FIG. 1.
It also should be assured that the overlap (Dovl) between the strap-outdiffusion 12 and a gate 20 of the vertical transistor 16 be sufficient to prevent the formation of xe2x80x9cbumpsxe2x80x9d in the electric potential of the channel of the transistor 16. These potential xe2x80x9cbumpsxe2x80x9d impede the channel current and degrade the electrical behavior of the transistor 16. It is to be assured that the edge of the strap outdiffusion (or strap diffusion) 12 be at least coincident with the edge of a gate conductor 22 in a worst case scenario. To meet this requirement, the thickness of the TTO (trench top oxide) 24, shown as parameter Ttto, should be sufficiently thin. However, if the TTO 22 is too thin the incidence of wordline to node shorts may be excessive. Modeling has shown that, for the currently practiced process, the maximum value of Ttto is limited by the diffusion to gate overlap requirement to approximately 30 nm. It may be necessary to use a thicker TTO for adequate reliability in conventional systems.
Therefore, a need exists for providing a strap diffusion for a vertical transistor in a trench storage cell which decouples the lateral outdiffusion (BSODx) from the diffusion to gate overlap (Dovl) and from the thickness of the TTO (Ttto).
A method for aligning a strap diffusion, in accordance with the invention, includes the steps of providing a trench in a substrate, the trench having a storage node formed therein including a buried strap on top of the storage node, and depositing a dopant rich material on the buried strap. A trench top dielectric is formed on the dopant rich material, and portions of the dopant rich material are removed above the trench top dielectric. Dopants are outdiffused from the dopant rich material into an adjacent region of the substrate to form the strap diffusion by forming a gate in an upper portion of the trench such that the strap diffusion is operatively disposed relative to the gate.
Another method for aligning a strap diffusion includes the steps of providing a trench in a substrate, the trench having a storage node formed therein including a buried strap on top of the storage node, depositing a dopant rich material on the buried strap, depositing a dielectric layer on the dopant rich material, forming a trench top dielectric on the dielectric layer, removing portions of the dopant rich material and the dielectric layer above the trench top dielectric and outdiffusing dopants from the dopant rich material into an adjacent region of the substrate to form the strap diffusion by forming a gate in an upper portion of the trench such that the strap diffusion is operatively disposed relative to the gate. The dielectric material may include a nitride having a thickness of between about 3 nm and about 15 nm.
In alternate methods, the dopant rich material preferably includes arsenic silicate glass (ASG), phosphorus silicate glass (PSG), or other insulating layer including these or other dopants, such as antimony. The step of depositing a dopant rich material on the buried strap may include the step of depositing the dopant rich material with a thickness of between about 5 nm and about 20 nm. The step of outdiffusing dopants may further include the step of forming a sacrificial oxide and a gate dielectric for forming the gate such that the dopants outdiffuse during processing. The dopant rich material and the trench top dielectric may form a top surface within the trench, the method may further include the step of forming a dielectric cap on the trench top dielectric and the dopant rich material at the top surface in the trench. The dielectric cap preferably includes a nitride. The trench may be include a trench storage capacitor or a buried bitline conductor in a cell using a stacked capacitor storage element.
A semiconductor device, in accordance with the present invention, includes a substrate having a trench therein. The trench has a storage node formed therein including a buried strap on top of the storage node. A dopant rich material is formed on the buried strap, and a trench top dielectric is formed on the dopant rich material. A strap diffusion is formed by outdiffusion of dopants from the dopant rich material into an adjacent region of the substrate. The adjacent region of the substrate is operatively disposed relative to a gate conductor formed in an upper portion of the trench.
In alternate embodiments, a dielectric cap layer may be formed on the trench top dielectric for preventing dopants from the dopant rich material from autodoping sidewalls of the trench. The dielectric cap layer preferably includes a nitride. The dopant rich material may include arsenic, phosphorous and/or antimony dopants. The dopant rich material may include a thickness of between about 5 nm and about 20 nm. The trench may be employed for a trench capacitor or a buried bit line. A nitride liner may be disposed between the dopant rich material and the trench top dielectric for blocking dopants from entering the trench top dielectric.